In charge of operating costs (OPEX), and a large part of operation cost is about 70% of the total cost, reduce the power it has to operators is urgently needed. Previously, chip providers to think of a way to through the transistor and process technology to reduce power consumption. Although transistor is the main reason for the power consumption of produce, but not the only factors, and through the transistor to reduce power consumption role is limited. Through the more comprehensive system level method can more effectively reduce the power consumption. Only the comprehensive consideration chip technology, give full play to the power of perception (power aware-which, in the role of the tools that code design considering low power consumption need to adjust the system architecture, the level, at the same time to significantly reduce the system level the power consumption of algorithm (such as in the remote rf head used in digital the predistortion application [DPD]), you can get the best results. Choose the right chip technology partners will make you benefit a lot from it. The best is the spirit by using the comprehensive and systematic measures to deal with the problem, and power management is not merely a narrow focus on the transistor and process node technology. ® Xilinx FPGA platform solutions can help design personnel adopts power optimization design and system level design and integration method to solve problems, overall power consumption. From the design level, the spirit of tools and best power perception wide range of low power consumption reference library and application design guidelines can help engineer the power consumption of the whole optimization. In addition, the best technology of superior spirit application engineer team also can help design personnel meet strict power consumption goals. The best engineers to help customers spirit gradually take design optimization techniques, such as folding DSP intensive design to shrink the size, etc, so as to use design size more small device to reduce the power consumption of the static and cost. From the system level level, the spirit of the attention of the best integration and also have the very good results. For example, in a single FPGA to highly integrated DuoGe division components can dramatically reduce system I/O, and significantly reduce the amount of power consumption. In addition, in the distance in the rf head DPD advanced algorithm can also make a telecommunications equipment manufacturer (TEM) use power consumption and costs are low power amplifier, which will bring about a big influence on the power consumption of the system level. Obviously, the best known to can't completely spirit to ignore the transistor and process node technology in reducing power loss function. And its former generation nano series 40 compared the best spirit, 28 nm 7 series will be the overall power consumption RuiJiang FPGA 50%. The transistor technology, the spirit of the thought process and low power consumption of DuoZhong transistor size of the use, can maximize reduce static power consumption. The best in spirit, memory and FPGA DSP SERDES use hard, with the same kind of this module competition DSP and other than the FPGA design maximize reduce the dynamic power consumption. The transistor level solve problems only to reduce the power consumption of the power consumption and operation cost saving a starting point, and only a comprehensive range of fine improvement all related aspects, can obtain the best results. Based on the spirit of the best FPGA design can make full use of the industry leading function density and senior radio algorithm (such as DPD) to minimize an external circuit and reduce power amplifier power consumption, and the entire system of power consumption will fall to lowest.
